UVM Wiki · Interactive source atlas
One environment.
Seven ways to understand it.
Explore a real generated SystemVerilog / UVM index. Every graph, connection, and phase is derived from the bundled sanitized source fixture.
HDL source files
UVM classes
Static relations
TLM connections
Start with architecture, then follow the evidence
Select demo_smoke_test, enter env, and expand the agent. The monitor publishes items to both the scoreboard and coverage. The driver uses the sequencer's item export. Click a wire or a class to see the relevant source.
Architecture
Follow test → env → agent and inspect the virtual-interface boundary.
Topology
Expand factory-created instances and jump to their source evidence.
Class Hierarchy
Explore inherited UVM component, object, and sequence types.
TLM Connections
Inspect item ports, exports, implementations, and connect calls.
Phase Map
Compare declared and inherited UVM phase implementations.
Wiki Graph
Explore local class relationships. Class Hierarchy also shows external UVM inheritance bases.
Code Explorer
Browse indexed definitions and the embedded source preview.
What this demo establishes
This is a static, per-file source index. It is not simulator elaboration or a passing simulation result. Runtime factory overrides, dynamic instances, and exact DUT/BFM binding need runtime evidence. UVM library definitions and uvm_macros.svh are external to the fixture; the filelist intentionally treats the UVM macro include as an external library include. The parser reports 49 per-file syntax diagnostics; this index is not compilation evidence.
The portable wiki embeds source context for graph and definition browsing. Full-text source search is an upstream serve-mode feature; the complete static source browser is available here for every bundled file.
Source revision: 82134333fab2a7a493cd5b13eac5709824c35202 · 0 unresolved project includes · Build and provenance notes · D3 license