SVIP AXI4 protocol checks
Author: syan
The passive monitor samples mon_cb (input #1step). It checks raw four-state values before building two-state transactions. These rule IDs are SVIP identifiers; they are not Arm checker rule names. cfg.checks_en gates protocol reports; cfg.x_checks_en separately gates X/Z reports. Reset terminates old assemblies and suspends normal checking.
| SVIP rule | Check |
|---|---|
| AXI-R01..R05 | AW/W/B/AR/R VALID and required payload remain stable while stalled |
| SVIP_AXI_B_DEP | BVALID requires a previously accepted AW and final W handshake |
| SVIP_AXI_R_DEP | RVALID requires a previously accepted AR handshake |
| AXI-R06 | W burst beat count and WLAST agree with AWLEN |
| AXI-R07 / R08 | BID/RID match a tracked request; same-ID queue head is used |
| AXI-R09 | RLAST agrees with the expected read beat count |
| AXI-R10 | INCR does not cross a 4KB boundary |
| AXI-R11 | WRAP has 2/4/8/16 beats and a beat-aligned start |
| AXI-R12 | AxBURST reserved encoding is rejected |
| AXI-R13 | AxSIZE does not exceed the configured DATA width |
| AXI-R14 | FIXED contains at most16 beats |
| AXI-R15 | Exclusive is non-FIXED, power-of-two total bytes, at most128 bytes/16 beats, aligned to total size |
| AXI-R16 | WSTRB never enables a byte outside the transfer's active lanes |
| AXI-R17 | No incomplete live request remains at end of test |
| AXI-R18 / SVIP_AXI_X | VALID/READY and valid channel control/active data do not contain X/Z |
| AXI-R19 | Optional incr_only port policy |
| AXI-R20 | Directional effective ID/address widths and complete burst extent |
| AXI-R21 | AxCACHE allocation bits require Modifiable |
| AXI-R22 | B/R EXOKAY requires the oldest matching request on that ID to have LOCK asserted |
AXI-R22 checks the first presentation of each B response or R beat, including a stalled beat that reset later discards. It is controlled by checks_en, independently of cov_en and transaction publication. Continued stalls are not repeatedly reported. An unknown or unmatched ID is owned by the X/dependency/matching rules. OKAY, SLVERR and DECERR on normal requests remain legal; exclusive EXOKAY and unsupported-exclusive OKAY remain legal.
Raw X/stability checks apply only where the protocol requires a meaningful value: WDATA uses asserted WSTRB lanes, RDATA uses active lanes. raw_inactive_x, raw_w_inactive_change, and raw_r_inactive_change protect against false positives. Channel analysis items retain four-state values. The monitor caches payloads within one sampled edge and saves only currently stalled channels. History is sampled even with checks disabled, so runtime re-enable compares against the latest stalled value. raw_checks_toggle exercises all five channels with READY low and X; exokay_id_order checks opposite LOCK values on one ID and active read lanes after request retirement.
The monitor tracks response dependencies against pre-edge state. An AW and B, or AR and R, appearing at the same sampled edge cannot satisfy the response dependency using that new request. Latency0 means the driver presents its response after the qualifying edge; it does not waive AXI dependencies.
Actual Arm BP063 Axi4PC.sv is separately installed and bound by checker/axi4pc/svip_axi_arm_checker.sv. The wrapper uses the same compile-time container definitions, enables protocol/X/end checks, and disables only the recommended maximum-wait policy. Its implementation is not distributed. Main acceptance runs use this checker. Deliberate monitor-only raw violations use exact scoped expected-report budgets; unmatched or excess reports still fail the runner. protocol_on/off retain an independent exact Arm error budget for the same deliberately illegal RDATA change.
The local Arm installation requires DATA_WIDTH32/64/128/256/512/1024. SVIP's configuration and runner accept that same AXI4 DATA set. Narrow transfers of1 or2 bytes remain legal on these buses. This separates DATA bus width from AxSIZE.
These checks plus the independent checker support the declared test profile. They are not a claim of formal AMBA certification, exhaustive checker equivalence, or verification of ACE/AXI5 extensions.