SVIP · Documentation + examples
Five verification domains.
A practical guide for each.
Browse complete user guides and architecture notes for AXI4, APB, JTAG, SPI, and Clock / Reset / Signal, with source examples for the documented APIs.
Protocol / control domains
Complete offline HTML guides
Original source examples
AXI4
Manager / subordinate / passive; independent read/write IDs, outstanding traffic, timing policies, and response ownership.
Browse source examples →APB3 / APB4
Requester and passive use; byte strobes, wait states, response checking, RAL, and practical control recipes.
Browse source examples →JTAG
Master / passive / optional TAP device; segmented scans, TDO masks, clock pause, and multi-TAP chain helpers.
Browse source examples →SPI
Standard four-wire master / slave / passive; modes 0–3, command-driven responses, timing, and validity masks.
Browse source examples →Clock · Reset · Signal
Reusable pin control; clock start/stop, reset epochs, signal capture, profiles, tieoff, fuse/strap, and IRQ.
Browse source examples →Choose an entry
Start with a user guide for initial integration and API contracts. Architecture pages explain ownership, timing, observations, and reset behavior. The APB cookbook and Control recipes organize practical tasks; AXI4 protocol checks list the monitor's explicit rules.
Author: syan · VCS / UVM 1.2 documentation snapshot · Revision b3347d005d05ef3dd88b8c45f1588540062e9f40