API recipes · Original source
Read the code behind the guides.
17 source examples copied from the source revision. These are reusable sequences and small example tops, with original SPDX and author comments retained.
The standalone Control tops use a small example receiver. Protocol sequences may refer to base sequences or independent peer fixtures from the full test suite. Those supporting runtime classes are not included. No example was simulated for this static publication. See runtime requirements.
AXI4
Manager / subordinate / passive; independent read/write IDs, outstanding traffic, timing policies, and response ownership.
- svip_axi_callbacks_example.svh · 32 lines
- svip_axi_controls_example.svh · 26 lines
- svip_axi_observation_example.svh · 36 lines
- svip_axi_patterns_example.svh · 38 lines
- svip_axi_reset_example.svh · 26 lines
- svip_axi_slave_model_example.svh · 50 lines
- svip_axi_timing_example.svh · 30 lines
APB3 / APB4
Requester and passive use; byte strobes, wait states, response checking, RAL, and practical control recipes.
- svip_apb_control_examples.svh · 137 lines
- svip_apb_examples.svh · 241 lines
JTAG
Master / passive / optional TAP device; segmented scans, TDO masks, clock pause, and multi-TAP chain helpers.
- svip_jtag_examples.svh · 40 lines
SPI
Standard four-wire master / slave / passive; modes 0–3, command-driven responses, timing, and validity masks.
- svip_spi_examples.svh · 53 lines
Clock · Reset · Signal
Reusable pin control; clock start/stop, reset epochs, signal capture, profiles, tieoff, fuse/strap, and IRQ.
- svip_clock_example.sv · 44 lines
- svip_reset_example.sv · 63 lines
- svip_signal_example.sv · 54 lines
- svip_clock_signal_example.sv · 40 lines
- svip_control_examples.svh · 142 lines
- svip_control_quickstart.sv · 52 lines