AXI to PCIe Packet Studio

Preset laboratory Typical examples

Choose an example to load its memory range and AXI/PCIe parameters.

Selected payload—

AXI burst decomposition—

PCIe TLP decomposition—

Selected address ranges—

Ingress AXI bursts—

PCIe request / completion TLPs—

Memory map

0 blocks

Viewport base

Cell size—

Visible span—

16 B / cell

SelectedAvailable64-bit paged address windowClick: one · drag down: sweep rows · wheel: addresses · middle-drag: pan

Global overview

No memory selected

0 bursts

AXI transfer map all controller-facing bursts

Selected payloadAXI burst coverageFocused burst

AXI data width AxSIZE (bytes / beat) Ingress max beats

AXI4 Read BurstsAxBURST = INCR · bursts never cross 4 KB

0 packets

TLP transfer map all request TLPs

Selected payloadTLP coverageFocused TLP

MPS MRRS RCB

4 KB is an absolute address boundary; MRRS and MPS are packet-size limits. Each box ends where the corresponding split is applied.

TLP split map

Request TLP headers

Completion TLP headers

Lineage Select an AXI transaction or TLP to trace its one-to-many mapping.