Bus Protocol Lab

Small visual tools for bus protocol learning and debug.

Static HTML demos Open directly in browser

AXI to PCIe Packet Studio

Select memory ranges, inspect their AXI4 burst decomposition, and follow the same payload into PCIe requests and completions across 4 KB, MPS, MRRS, and RCB boundaries.

AXI4 bursts PCIe TLPs 64-bit memory map standalone HTML

PCIe TLP Split Demo

Visualizes Memory Read Request splitting, byte-enable behavior, and Completion with Data splitting under MRRS, MPS, RCB, and 4 KB boundary constraints.

MemRd request CplD completion 4KB split

AXI Atomic Demo

Interactive AXI4 atomic byte-lane view for memory selection, DNOC internal reqdata placement, and IP-facing AXI wstrb/wdata placement.

Format table clickable cells byte lanes