PCIe TLP Split Protocol Demo

Type a byte address and a byte count. The page shows how PCIe turns that range into DW-aligned MemRd requests with FBE/LBE, then into CplD chunks with Byte Count and Lower Address.

Read request split: MRRS + 4KB Completion split: MPS + RCB + 4KB
Requested bytes-
MemRd TLPs-
CplD TLPs-
Request overhead-

Address coverage

MemRd split. Each tile is one aligned DW. Green byte lanes mean BE=1.
CplD split. Same DW grid; green byte lanes are valid returned bytes.

MemRd TLPs

Click a card to inspect its DW envelope and byte-enable pattern.

CplD TLPs

Click a card to inspect the returned Byte Count and Lower Address.

Selected TLP

Split logic

DW envelope

Green means enabled/valid. Dark bytes are masked in a request or padded in a completion.
MemRd request fields
PCIe read requests are DW-oriented. The address field is DW aligned, while FBE/LBE describe the real byte window in the first and last DW.
Completion fields
Completions use Byte Count and Lower Address, not BE. The data payload may still occupy a partial last DW.
4KB rule
Read requests do not cross a 4KB boundary. Completions also stop at a 4KB boundary.
What the colors mean
Green byte lanes are enabled by BE or returned as valid completion bytes. Amber marks 4KB page starts.